(i) Field of the Invention
The present invention relates to a multi-value logic device for transmitting or receiving multi-value logic signals, a bus system in which multi-value logic devices are connected with a shared bus, and a network system in which information processors loaded with multi-value logic devices are connected with a shared network, and especially to suppression of enlargement of equipment with a multi-value logic device mounted thereon and enhancement of throughput.
(ii) Description of the Related Art
A computer or other information processor is loaded with semiconductor integrated circuits or other devices, and the devices usually perform data transfer via a shared bus. Recently, with the development of semiconductor technology, an on-device circuit has been highly integrated, memory capacity has been enlarged, and the processing capability of a processor or the like has been improved. As a result, the data amount transferred between the devices is progressively increasing. In general, since the data transferred via the bus is binary, the number of bus signal conductors (bus width) is also progressively increasing to handle the increased data amount. It is natural nowadays to set the bus width to 32 bits or 64 bits, and even a bus width of 128 bits is going to be placed on the market. Therefore, with the increase of bus width and, accordingly, with the increase of the number of pins or wiring, the enlargement of a device, a board loaded with the device and further an equipment itself loaded with the board, the deterioration of reliability due to complicated wiring, or the cost increase, has caused problems.
To solve the problems, there is proposed a technique in which a plurality of bus masters can be simultaneously connected. In a bus system using a shared bus, a bus master which exclusively uses the bus shared by a plurality of devices is usually selected, and only the bus master can be used for a certain time. In this case, by recognizing the presence of a plurality of subordinate bus masters in predetermined conditions, simultaneous/parallel data transfer is realized. Thereby, data throughput is prevented from decreasing without increasing the number of signal conductors.
However, in the technique in which the transfer of binary data is a prerequisite, the bus width cannot be reduced. To solve this problem, there is proposed a system using a multi-value logic bus in which binary data is converted into analog signals to prepare a multi-value logic signal and perform data transfer, so that the number of signal conductors can be reduced and wiring is facilitated. For example, a method is disclosed in Japanese Patent Laid-Open Publication No. Hei 1-14631, in which a device output section is provided with a D/A converter while an input section is provided with A/D converter, and data is transferred with an analog signal having a multi-value level on a bus. The operation of multi-value logic bus system in an analog system will be described in detail with reference to a system structure shown in FIG. 11.
In FIG. 11, each of devices A, B, C, D connected via a bus uses a plurality of bus levels 1, 2, 3 in a fixed manner. For example, when binary data is 1 (high level), the data is converted to a voltage of 1V at bus level 1, the data is converted to a voltage of 2V at bus level 2, and the data is converted to a voltage of 4V at bus level 3. If 0V is included, data can be represented by eight voltage amplitudes for each signal conductor. Therefore, the system can reduce the number of signal conductors compared with the binarizing system in which two voltage levels are used for each signal conductor. When data of 15 bits is transferred using the aforementioned bus levels 1 to 3, different from the binarizing system in which 15 data signal conductors are necessary, data transfer can be performed only with five data signal conductors in the analog multi-value system. As a result, since the number of signal conductors can be reduced using a multi-value logic signal, the aforementioned problems such as the increase of the bus width, the increase in the number of pins and wiring, and the enlargement of the device, the bus system using the device, and the like can be solved.
In the bus system in which conventional multi-value logic devices are connected, however, since the devices use the same bus levels in the system, communication cannot be executed simultaneously with other communication to avoid mutual interference as long as the shared bus is used. Specifically, in the conventional art, although the number of signal conductors can be decreased and the size of the board or the like can be reduced, communication can be simultaneously executed only between a pair of devices. Therefore, multiplex communication by a plurality of bus masters is impossible, so that throughput cannot be enhanced.